1. Field of the Invention
The present application relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a gate-in-panel (GIP) type liquid crystal display (LCD) device and a method of fabricating the array substrate.
2. Discussion of the Related Art
As information age progresses, flat panel display (FPD) devices having light weight, thin profile, and low power consumption have been substituted for cathode ray tube (CRT) devices. Liquid crystal display (LCD) devices, plasma display panel (PDP) devices, field emission display (FED) devices, and electroluminescent display (ELD) devices are examples of the FPD devices. Since the LCD devices have excellent characteristics in resolution, contrast ratio, color display and display quality, the LCD devices have been widely used in a notebook computer, a monitor and a television.
In general, an LCD device includes two substrates spaced apart and facing each other and a liquid crystal layer interposed between the two substrates. Each of the two substrates includes an electrode on a surface facing the other of the two substrates. A voltage is applied to each electrode to induce an electric field between the electrodes. The arrangement of the liquid crystal molecules as well as the transmittance of light through the liquid crystal layer is controlled by varying the intensity of the electric field, thereby the LCD device displaying images using the change in light transmittance.
The LCD device includes a liquid crystal panel having two substrates and a liquid crystal layer between the two substrates, a backlight unit under the liquid crystal panel and a driving circuit unit connected to the liquid crystal panel and the backlight unit. The driving circuit unit includes a printed circuit board (PCB), a gate driving circuit supplying a gate signal to a gate line of the liquid crystal panel and a data circuit supplying a data signal to a data line of the liquid crystal panel. The gate driving circuit and the data driving circuit are formed as a tape carrier package (TCP) connected to the liquid crystal panel. For example, the gate TCP including the gate driving IC may be connected to a gate pad on the liquid crystal panel and the data TCP including the data driving IC may be connected to a data pad on the liquid crystal panel. The gate and data pads are connected to the gate and data lines, respectively.
Since weight and volume of the LCD device increase due to the gate TCP and the data TCP, a gate-in-panel (GIP) type LCD device where the gate driving circuit is formed in the liquid crystal panel and only the data TCP is connected to the liquid crystal panel has been suggested.
FIG. 1 is a cross-sectional view showing a gate-in-panel type liquid crystal display device according to the related art.
In FIG. 1, a gate-in-panel (GIP) type liquid crystal display (LCD) device 1 includes a first substrate 10, a second substrate 50 and a liquid crystal layer 70. The first and second substrates 10 and 50 face and are spaced apart from each other, and the liquid crystal layer 70 is interposed between the first and second substrates 10 and 50. The first and second substrates 10 and 50 include an active area AA displaying images and a non-active area NA surrounding the active area AA.
A gate line (not shown) and a data line 28 are formed on an inner surface of the first substrate 10 in the active area AA. The gate line and the data line 28 cross each other to define a pixel region P. A pixel thin film transistor (TFT) Tp connected to the gate line and the data line 28 is formed in each pixel region P. The pixel TFT Tp includes a gate electrode 15, a gate insulating layer 21, a semiconductor layer 23, a source electrode 30 and a drain electrode 32. The gate electrode 15 is connected to the gate line, and the gate insulating layer 21 is formed on the gate electrode 15. The semiconductor layer 23 on the gate insulating layer 21 includes an active layer 23a and an ohmic contact layer 23b, and the source and drain electrodes 30 and 32 on the semiconductor layer 23 are spaced apart from each other. The source electrode 30 is connected to the data line 28. A passivation layer 38 is formed on the data line 28, the source electrode 30 and the drain electrode 32, and a pixel electrode 43 is formed on the passivation layer 38. The passivation layer 38 includes a drain contact hole 41 exposing the drain electrode 32 and the pixel electrode 43 is connected to the drain electrode 32 of the pixel TFT Tp through the drain contact hole 41.
A gate driving circuit (not shown) including a plurality of circuit units (not shown) and an electrostatic discharge circuit between the adjacent circuit units are formed on the inner surface of the first substrate 10 in the non-active area NA. Each of the plurality of circuit units and the electrostatic discharge circuit includes a driving TFT Td having a gate electrode 16, the gate insulating layer 21, a semiconductor layer 24, a source electrode 34 and a drain electrode 36. The passivation layer 38 is formed on the driving TFT Td.
In addition, a black matrix 53 is formed on an inner surface of the second substrate 50. The black matrix 53 includes a first black matrix 53a having openings in the active area AA and a second black matrix 53b in the non-active area NA. A color filter layer 58 including red, green and blue color filters 58a, 58b and 58c is formed on the inner surface of the second substrate 50 and the first black matrix 53a in the active area AA such that the red, green and blue color filters 58a, 58b and 58c correspond to openings of the first black matrix 53a. A common electrode 60 is formed on the second black matrix 53b in the non-active area NA and the color filter layer 58 in the active area AA.
The liquid crystal layer 70 is formed between the pixel electrode 43 and the common electrode 60. Further, a seal pattern 80 is formed between the passivation layer 38 and the common electrode 60 in the non-active area NA, and a column spacer 63 is formed between the passivation layer 38 and the common electrode 60 in the active area AA to correspond to the first black matrix 53a. 
FIG. 2 is a plan view showing a driving thin film transistor of a gate-in-panel type liquid crystal display device according to the related art.
In FIG. 2, a driving thin film transistor (TFT) Td of each of a plurality of circuit units and an electrostatic discharge circuit in a non-active area NA includes a gate electrode 16, a semiconductor layer 24, a source electrode 34 and a drain electrode 36. Each of the gate electrode 16 and the semiconductor layer 24 has a plate shape. In addition, each of the source electrode 34 and the drain electrode 36 has a comb shape including a horizontal portion 34a and 36a and a plurality of vertical protrusions 34b and 36b extending from the horizontal portion 34a and 36a. The plurality of vertical portions 34b of the source electrode 34 alternate with the plurality of vertical portions 36b of the drain electrode 36. Furthermore, the plurality of vertical portions 34b of the source electrode 34 are spaced apart from the plurality of vertical portions 36b of the drain electrode 36 to define a channel region CH as a current path. The channel region CH has a channel width W and a channel length L. Since the driving TFT Td in the non-active area NA is required to have a relatively high on-current, the driving TFT Td is formed to have a relatively great channel width W of the channel region CH and have a relatively great size of the gate electrode 16 covering the channel region CH. As a result, most of the non-active area NA is occupied with the driving TFT Td having a relatively great size.
The GIP type LCD device 1 is fabricated through a first process of forming the pixel TFT Tp, the driving TFT Td and the pixel electrode 43 on the first substrate 10, a second process of forming the black matrix 53, the color filter layer 58 and the common electrode 60 on the second substrate 50, and a third process of attaching the first and second substrates 10 and 50 and forming the liquid crystal layer 70 between the first and second substrates 10 and 50. The third process may be referred to as a cell process. For example, the cell process may include a step of forming alignment layer on each of inner surfaces of the first and second substrates 10 and 50, a step of forming a cell gap by attaching the first and second substrates 10 and 50, a step of cutting the attached first and second substrates 10 and 50 into unit cells, and a step of injecting liquid crystal materials into each unit cells.
After the first and second substrates 10 and 50 are attached to each other using the seal pattern 80 and the attached first and second substrates 10 and 50 are cut into the unit cells, the liquid crystal materials may be injected into each unit cell in a vacuum state cell through an injecting method using a capillary phenomenon. However, the process time for forming the liquid crystal layer by the injecting method may be over about 10 hours.
To reduce the process time for forming the liquid crystal layer, a method using a vacuum dispensing and attaching apparatus has been suggested. In the method using the vacuum dispensing and attaching apparatus, the steps of dispensing and attaching are performed under a vacuum state. For example, after a seal pattern of ultra violet (UV) curable sealant is formed on one of the first and second substrates, the liquid crystal materials are dispensed onto the one of the first and second substrates. Next, the first and second substrates are aligned and attached, and a UV ray is irradiated onto the seal pattern for curing or hardening. Next, the attached first and second substrates are cut into a plurality of unit cells. Since the liquid crystal layer is formed by a dispensing method instead of an injection method, the process time for forming the liquid crystal layer is reduced. In addition, the seal pattern has a closed loop shape without an injection hole for the liquid crystal materials.
After the first and second substrates are attached, the UV ray is irradiated through the first substrate because the second substrate has a blocking pattern such as a black matrix at a portion corresponding to the seal pattern for preventing light leakage. For example, the ratio of an open area that does not include the blocking pattern to the whole area of the first substrate corresponding to the seal pattern may be required to be over about 50% for curing the seal pattern by the UV ray. In addition, as shown in FIGS. 1 and 2, since the driving TFT Td in the non-active area NA of the first substrate 10 of the GIP type LCD device 1 has a relatively great size, the UV ray does not passing through the non-active area NA of the first substrate 10 corresponding to the gate driving circuit. As a result, when the seal pattern 80 and the liquid crystal layer 70 is formed through the method using the vacuum dispensing and attaching apparatus in the GIP type LCD device 1, the seal pattern 80 is insufficiently cured. The insufficiently cured seal pattern 80 contacts and contaminates the liquid crystal layer 70.